Radio Frequency (RF) measurement systems typically include detector circuits to measure parameters such as power. One type of detector circuit is a logarithmic amplifier (“log amp”) which generates an output signal VOUT that is related to its input signal VIN by the following function:VOUT=VY log(VIN/VZ)  Eq. 1where VY is the slope and VZ is the intercept as shown in idealized form in FIG. 1. Progressive compression type log amps achieve the logarithmic transfer function through the combined effect of multiple gain stages and detector cells that approximate a logarithmic law.
FIG. 2 illustrates a prior art progressive compression log amp which includes a series of cascaded gain stages 10, each of which has a relatively low linear gain up to some critical level. Above the critical level, the gain of each stage is limited to a lower level—in some cases to zero. Thus, they are also referred to as amplifier/limiter stages. A series of detector cells 12 are connected to corresponding gain stages. The outputs of the detector cells are added together to generate the log output signal. In this example, the detector cell outputs are current mode signals, so they can be added together through a simple summing connection at node N1.
FIG. 3 illustrates a prior art detector cell based on three transistors arranged as a rectifying transconductance (gm) cell. The emitter areas of the transistors are ratioed; that is, transistors Q1 and Q3 have a unit emitter area of “e”, while transistor Q2 has an emitter area of D times e. The input signal is applied across the bases of Q1 and Q3 as a differential voltage VIN. The base of Q2 is held at the midpoint of the input signal by the divider formed by input resistors RB.
The bias current IT (also referred to as a quiescent or tail current) through transistors Q1-Q3 is generated by a bias transistor QA. The level of bias current IT is determined by the voltage applied to the base of QA. An operational amplifier (op amp) 14 maintains the base of QA at the voltage VREF which is typically generated by a precision voltage reference. The same reference voltage is also applied to the bases of additional bias transistors QB, QC, etc., which provide the same bias current to the other detector cells.
The collector currents of Q1 and Q3 are summed together to form one detector output current IP, while the collector current of Q2 provides another output current IN. Either or both of the output currents may be used to generate the final logarithmic output. If IP is used as the sole output signal, the current IN may be diverted to a positive power supply VP, and the output current IP has the form shown in FIG. 4. I0 is the output current when the input signal is zero, that is, VIN=0. IL is the limit of the signal available from the detector cell when the input signal is large. Thus the maximum current swing M available at the detector output is M=IL−I0 and is related to the bias current IT and the emitter area ratio D.
FIG. 5 illustrates the detector cell output current IP in logarithmic form for several detector cells in a progressive compression log amp in which each detector cell is implemented using the IP output from the circuit of FIG. 3. The curves are shown as a function of the log input signal LOG INPUT on a logarithmic scale. The right-most curve in FIG. 5 is for the first detector cell, the next curve is for the second detector cell, etc. Each curve is offset relative to the others because the input VIN to any specific detector cell is shifted relative to the main LOG INPUT signal depending on its location along the cascade of gain stages. Thus, each curve is offset from its adjacent curve by an amount that is related to the gain A of each gain stage 10. Assuming each detector cell is fabricated using identical components on an integrated circuit, IL, I0, and M will be essentially identical for each detector cell.
FIG. 6 illustrates the final output signal obtained by summing together the output currents IP from all of the detector cells. The final output signal approximates the ideal log function shown in FIG. 1. Since each of the individual curves shown in FIG. 5 has the same maximum output swing M, the slope of the final output signal is strongly dependent on the value of M which determines the height of each of the piecewise linear approximation sections in the final output function.
Referring back to FIG. 3, if the other output current IN is used to generate the final logarithmic output, IP may be diverted to the power supply, and the IN output has an inverted shape as shown in FIG. 7. In this case, summing together the IN outputs from all of the detector cells produces a final log output signal having a negative slope as shown in FIG. 8. Note that in either case, the relative vertical position of the individual curves in FIGS. 5 and 7 generally does not affect the log slope. That is, a DC offset may be added to the curves in FIGS. 5 and 7 to shift them up or down without affecting the maximum output swing M that determines the slope of the final logarithmic output.
Another type of detector circuit is based on a variable gain amplifier (VGA) arranged to drive one of a pair of detectors, for example, a pair of squaring cells arranged to implement a “difference of squares” function. FIG. 9 illustrates a prior art power detection circuit that includes a VGA 15 and two identical squaring cells 16 and 18. The VGA amplifies the input signal VIN with a gain determined by a gain control signal VG. The output from the VGA drives squaring cell 16 which generates an output signal (or squared signal) ISQR. A DC reference signal VREF is applied to squaring cell 18 which generates IREF. A nulling circuit 20 generates the final output signal VOUT in response to ISQR and IREF. The circuit of FIG. 9 can be configured for operation in a measurement mode, in which case the final output signal VGUT is fed back to the VGA and used as the gain control signal VG. It can also be configured in a controller mode, in which case the final output signal \Tour is used to control the gain or power of a device such as a power amplifier. In controller mode, a sample of the output from the power amplifier is fed back to the input terminal of the VGA as the input signal VIN, and the control signal VG is then used as a set-point signal. In either mode, the system servos until the average of ISQR equals IREF.
Since detector circuits are used in measurement systems, accuracy is a primary concern. However, a variety of factors tend to degrade the accuracy of detectors. For example, variations in operating frequency and temperature tend to cause the actual detector output to deviate from the ideal output, as do variations in power supply voltage. Differences in device characteristics due to variations in manufacturing processes also introduce errors.
In a monolithic integrated circuit (IC) implementation of a progressive compression log amp, temperature compensation of the slope VY is typically provided by utilizing proportional to absolute temperature (PTAT) bias currents for the gain and detector cells since those are the structures that determine the slope. Temperature stabilization of the intercept VZ is typically provided at the front or back end of the log amp, for example, by interposing a passive attenuator with a loss that is proportional to absolute temperature (PTAT) between the signal source and the log amp. Another technique for temperature compensating the intercept of a log amp involves adding a carefully generated compensation signal to the output so as to cancel the inherent temperature dependency of the intercept. See, e.g., U.S. Pat. No. 4,990,803; and Barrie Gilbert, Monolithic Logarithmic Amplifiers, August 1994, §5.2.4.
Frequency compensation for log amps may also be problematic. For any given operating frequency, a predetermined compensation signal may be added to the output, thereby providing an accurate output at the given frequency but resulting in unacceptable errors at other frequencies. This problem may be compounded by “peaking” in the frequency response which causes non-monotonic behavior of the compensation. That is, the value of the required compensation signal may initially increase as the operating frequency increases, but a peak may be reached, at which point the value of the required compensation signal begins decreasing with further increases in operating frequency. Thus, the required compensation may be a nonlinear function.
Temperature and frequency compensation for a power detection circuit having a VGA and difference of squares detectors may present similar problems. Although the use of identical squaring cells may provide temperature compensation to the detector cells, the DC reference signal VREF shown in FIG. 9 causes the second squaring cell to dwell at a single DC operating point that provides no frequency-related contribution to its compensation effects. If the circuit of FIG. 9 is used in a control configuration for an input signal having a carrier frequency that is modulated by a baseband signal, then some amount of frequency compensation may be achieved by applying the baseband modulation signal as the VREF input to the second squaring cell. See, e.g., U.S. Pat. No. 6,429,720. This technique, however, requires prior access to the baseband modulation signal.